With the rapid development of Ultra Large Scale Integration (ULSI) technique, integrated circuits (ICs) manufacturing techniques become more and more complex and precise. In order to improve an integration degree and reduce a manufacturing cost of a device, the Feature Size of components becomes smaller and smaller, and the number of components per unit area in a chip becomes higher and higher. Therefore, it is difficult to meet the requirement for intense distribution of components by single-layer routing; multi-layer routing technique has been employed to utilize vertical space in a chip so as to further improve the integration degree of device. However, the multi-layer metallization results in unevenness on the surface of the wafer and is severely disadvantage for patterning. In order to implement a multi-layer metallization structure on a wafer with a large diameter, it is required to achieve a good overall flatness on each layer in the wafer, i.e., it is required a planarization process for a layer, such as conductor, ILD (Inter-Layer Dielectric), metal (e.g., W, Cu, Al) silicon oxide, and nitride etc., in the multi-layer interconnection structure.
Now, Chemical Mechanical Polishing (CMP) is a commonly planarization method in wafer planarization process; however, latest investigations show that, the wafer surface flatness achieved by a conventional CMP can't meet the requirement for some applications, such as an application in optical instruments, an application in image transmission or image processing components and other products with a high requirement for surface quality, and the yield of the products is very low, due to the extremely high requirement for wafer surface flatness.
For example, during the planarization for a top metal layer in Liquid Crystal on Silicon (LCOS) technique, the top metal layer 40 needs to be divided into several small mirrors, as shown in FIG. 1A, in which reference number 10 represents the ILD layer, reference number 20 represents the intermediate metal layer, reference number 30 represents the contact hole metal, and reference number 40 represents the top metal layer. Therefore, as shown in FIG. 1B, the top metal layer 40 and the ILD layer 10 are etched to a certain depth to form a trench 50; then, as shown in FIG. 1C, an insulating oxide layer 60 is deposited over the trench 50 and the top metal layer 40 to fill the trench 50; next, as shown in FIG. 1D, the insulating oxide layer 60 over the top metal layer 40 is polished by a CMP process; finally, the entire insulating oxide layer 60 on the top metal layer 40 is removed by a dry etching process to form a structure as shown in FIG. 1E. However, by means of a microscopic surface analysis, it is found that the top metal layer 40 formed by the above method has concentric ring recesses on the surface, as shown in FIG. 2, which causes the top metal layer 40 unable to be used as the mirror of LCOS.
Further investigation shows that the concentric ring recesses on the top metal layer 40 is caused by concentric ring recesses on the surface of the polishing pad used in conventional CMP technique. For example, in a polishing pad structure described in China Patent Application CN03140681, a surface of the polishing pad has grid, ring, or helix recesses, as shown in FIG. 3. Since the surfaces of the polishing pads have recesses, the recesses similar to that in the polishing surface will be formed on the surface of the top metal layer 40 during CMP process, hence, degrading surface flatness of the top metal layer 40.